The advent of digital technology and the rapid development of microprocessor technology gave rise to a demand for programmable logic. A PLD (“programmable logical device”) is an integrated circuit whose logic function is defined by the user by means of programming. A PLD is an architecture for digital logic operations with a plurality of switches that enable a multiplicity of signal paths. The logic function assigned to a PLD in a user-specific fashion is defined by means of the configuration of the PLD.
PLDs include, inter alia, field-programmable gate arrays (FPGAs), the functionality of which can be assigned to them by the user, and mask-programmable gate arrays (MPGAs, also called “structured ASICs”), which can be allocated a logic function by means of hardware configuration. Via-programmable gate arrays (VPGAs) belong among MPGAs.
A digital logic cell maps n input signals onto an output signal. The number of possible mapping functions is 22n. A circuit group as a digital logic cell is realized in accordance with the prior art by using so-called look-up tables (LUT), for example. For this purpose, function values of the logic function are set by means of a data word of 2n bits. In other words, the respectively selected logic function is coded into a data word. n input signals a0, a1, . . . , an−1 are combined with one another in accordance with the selected logic function. Consequently, the logic input signals of the logic function y=f (a0, a1, . . . , an−1) may be regarded as a binary address and converted into a one-hot coding in order to select the function value subsequently by means of pass gate logic. Such a method is disclosed in Wannemacher, M “Das FPGA-Kochbuch” [“The FPGA cookbook”], FIG. 6.4: SRAM cell from XILINX, 1st edition, International Thomson Publishing Company, Bonn, 1998, page 111, for example.
As an alternative, the inputs may serve as control inputs for a multiplexer tree, see Wannemacher, M “Das FPGA-Kochbuch” [“The FPGA cookbook”], FIG. 7.36: logic block (CLB) of the XC4000 families, 1st edition, International Thomson Publishing Company, Bonn, 1998, page 197. The multiplexers may be realized in a logic-based manner and/or on the basis of transmission gates.
U.S. Pat. No. 6,529,040 B1 discloses an FPGA on the basis of a look-up table (LUT).
The logic basic cells using a look-up table which are disclosed in the prior art have disadvantages with regard to switching speed and/or interference immunity. The known solutions furthermore cannot be realized sufficiently compactly in terms of layout for many applications. Therefore, continued scaling is possible only with difficulty using the LUT solutions disclosed in the prior art.
As an alternative to the known LUT architectures, the prior art discloses interconnections comprising individual logic gates which can be used to form a desired logic function. However, such an architecture is restricted to the formation of a very specific logic function, whereas the overall scope of all possible logic mapping functions can only be realized in a very complicated manner using predetermined logic gates. The complicated logic gates are restricted with regard to the achievable switching speed, too. The limitation of the scope of the possible logic functions considerably complicates the automatic logic partitioning in the case of an FPGA design.
Another approach consists in making complex logic gates, which realize a combination of a plurality of logic inputs, flexibly interconnectable and in accomplishing a complete or almost complete coverage of the combinatorial function space through skillful combination of fewer than the possible inputs. However, such a realization has the disadvantage that flexibility outside the cell is used for the internal logic configuration of the cell and is thus limited. Moreover, the functional mapping is generally complicated.
Furthermore, U.S. Pat. No. 5,592,107 discloses a configurable NAND/NOR element.